Authors - Hetansh Shah, Himangi Agrawal, Dhaval Shah Abstract - The paper outlines the design, implementation, and evaluation the SHA-256 cryptographic hash function on an FPGA platform, focusing on its use in Bitcoin mining. SHA-256 is a key part of the Bitcoin system, generating unique hash values from data to keep it secure and intact. The goal was to create a fast and low resource utilized, hardware-based version of SHA-256 using VHDL and implement it on the Zed- Board FPGA development platform. The main focus was on the VHDL implementation, making it modular and pipelined to improve speed and efficiency regarding resource utilization. The Zed-Board features the Xilinx Zynq-7000 SoC has been considered for hardware implementation. The design also included message buffering, preprocessing, and a pipeline for hash computation, allowing the system to handle incoming data in real time while producing hash outputs quickly. The algorithm’s functionality was verified using simulation tools in Xilinx Vivado, and the hardware implementation results were compared to previous works. It is clearly depicted the proposed method utilizes fewer resources as compared to the previous works while maintaining a throughput 27% greater than the software solution. The hardware design significantly outperforms software as well as SW/HW (HLS) versions in speed and energy use. The total on-chip power utilized was 12.898 W.
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