Authors - Shubham Garg, Kanika Monga, Nitin Chaturvedi, S. Gurunarayanan Abstract - Approximate computing has emerged as a promising paradigm for error- tolerant AI/ML applications deployed on energy-constrained edge devices. It has gained significance for edge devices due to its potential to reduce power consumption. In conventional computing systems, implementing computationally intensive machine learning algorithms results in large power consumption. Addressing this challenge, the complexity of hardware computing units can be reduced by optimizing the circuit logic while slightly trading off the computational accuracy. This technique is termed as Approximate computing where the circuit provides close-to-accurate results rather than precise results with significant reduction in power consumption. Therefore, in this work, we propose two approximate adder configurations that utilize novel logic optimization techniques to lower the power consumption and the hardware complexity of the circuit. The proposed approximate adders are designed using 55 nm technology and evaluated based on power consumption, delay, area, and power delay product (PDP). The simulation results indicate a reduction of 46.9% and 57.21% in power consumption for the approximate adder-1 & adder-2 compared to the conventional full adder. Furthermore, to validate the reliability of the proposed design, we also evaluated and calculated the accuracy metrics in terms of mean error distance (MED) of 0.25, which reflects the error tolerance of the proposed design.
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