Authors - Pranav Indurkar, Mansi Dangade, Apoorva Kumar, Harsh Thakar Abstract - This paper explores the chip implementation of a low-power RSA encryption system, optimizing resource and Power usage while maintaining the security. The RSA Algorithm modeled using Verilog, implemented on the XILINX SPARTAN-7 FPGA (XC7S50-CSGA324-2) with a comparative analysis of 4- bit to 8-bit algorithmic parameters (such as p, q, e, d, M, C, n, phi_n). Two approaches are studied: one with uniform bit sizes of algorithmic parameters and another with smaller p & q bit sizes. Results show that the second approach yields better efficiency. Future work with CADENCE CIC tools will further optimize power consumption. This work offers insights into designing low-power RSA encryption chip for modern digital systems.
