Authors - Hepin Gondaliya, Parth Monpara, Dhaval Shah Abstract - Multiplier is a crucial factor influencing processor performance, making its optimization vital for efficient computing. This paper introduces a multiplier design that achieves remarkable improvements, reducing resource utilization by more than half, logic delay to nearly a quarter and total power consumption to less than a quarter of compared to conventional radix-2 booth’s multiplied The proposed design was synthesized and implemented using Xilinx Vivado on a Zedboard FPGA, demonstrating its effectiveness and scalability for modern FPGA-based systems.. . .
